A verification methodology for large mixed-signal SoC designs using NanoSim-VCS

With the increased emphasis on trimming production costs and time to market, first-pass silicon success has become a fundamental requirement for system-onchip (SoC) designs. First-pass silicon success can only be achieved through a comprehensive methodology for verifying the functional, timing, and analog/digital signal interface of a design. This article addresses the challenges associated with verifying large mixed-signal system-on-chip (SoC) designs and offers a detailed verification methodology using the NanoSim integration with VCS from Synopsys. This article also presents the results achieved on a mixed-signal SoC design using this verification methodology.